RAM macros and the like which are embedded within LSI chips are necessarily surrounded by intervening circuitry including, for example, logic elements, and input/output chip interfaces. As a result, the embedded macros are not directly accessible from the input and output terminals of the chip. The intervening circuitry causes on-chip time delays to be associated with input and output signals of the chip. These delays prohibit accurate timing measurement between, for example, macro-enable signals and test input/output signals during a macro performance test, since the associated time delay for a given signal is unknown.
Various methods and devices exist which compensate for the on-chip time delays. These macro performance test methods and devices usually include complicated elements which bypass the intervening circuitry so that the macro is directly accessible from primary inputs.
U.S. Pat. No. 3,961,251 discloses a large scale integrated chip or semiconductor device for testing embedded arrays. The array includes address gates, data-in gates and data-out gates, and the device includes wiring that skirts the logic circuitry of the device, thereby allowing direct access from the primary input to the array.
U.S. Pat. No. 3,961,254 discloses a semiconductor device for testing embedded memory arrays. The device includes means for introducing information directly into the address register and data register from primary inputs, thereby bypassing the associated logic circuitry. The device further includes means which inhibit the associated logic circuitry during the testing mode. The information scanned into the registers is scanned out to determine whether there is a defect in the registers.
U.S. Pat. No. 4,481,627 discloses a method for testing memory arrays embedded within electronic assemblies. More particularly, the method includes isolating the embedded memory from other logic elements, and then testing the embedded memory array with a memory test subsystem.
In addition, there exist various scanning. recirculating and comparing methods for determining defective memory arrays and macros.
U.S. Pat. No. 4,332,028 discloses a method and device for measuring the memory address access time (AAT) of RAM or ROS memories by utilizing a data recirculation technique. The recirculation technique includes measuring the oscillation frequency of the memory, and then determining the required address access time.
U.S. Pat. No. 3,961,252 discloses a semiconductor device for testing embedded memory arrays. In the device, address and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit. The device further includes a feedback circuit for recirculating the counter outputs to address and data register inputs.
U.S. Pat. No. 4,510,603 discloses a system for testing the access time of a ROM semiconductor memory. The system includes means for splitting the output data of the memory into two paths. One path is used to temporarily hold the memory output data for a specified time interval after which it is compared with the same memory output data on the second path. If the two paths do not contain the same memory output data, a comparator circuit generates an error signal.
U.S. Pat. No. 4,058,767 discloses a device for determining the AC or switching delay behavior of an LSI circuit. The device measures the signal propagation along different circuit paths to determine the AC characteristics.
U.S. Pat. No. 4,503,387 discloses a test for the AC characteristics of the input and output circuitry of programmable arrays independent of the AND or OR matrices. The test includes disabling the AND matrices, and connecting the true and complement outputs of all of the input buffers to each of the output buffers.
U.S. Pat. No. 4,225,957 discloses a testable LSI chip having macros embedded therein. The chip includes connecting the macros so that the total chip can be tested by testing each macro individually.
U.S. Pat. No. 4,482,953 discloses a microprocessor having a programmable logic array (PLA). The PLA is operable for supplying a sequence of instructions which will test various elements in the microprocessor.
U.S. Pat. Nos. 4,461,000 and 4,513,418 are cited as further examples of methods and devices for determining defective LSI components.
As indicated above, many of the previous macro performance test methods and devices include complicated elements which are implemented on the macro. In addition, many of these test methods and apparatus limit the size or type of macro which can be tested.